Programmable devices such as electrically erasable programmable read only memories (EEPROMs), flash memories, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable array logic (PAL), field programmable gate arrays (FPGAs), etc., typically include non-volatile memory elements which can be programmed or erased under the control of appropriate programming or erase voltages. When programming or erasing such devices, the programming or erase voltage is typically applied to the non-volatile memory element for a period of time (a programming or erase pulse width) sufficient to achieve the desired programming or erasing of the memory cell. In the past, it was common to use a fixed programming or erase pulse width, e.g., as may be specified by a manufacture of the programmable device.
FIG. 1 illustrates a conventional programming operation 100 for a programmable device. The operation begins at step 102 where the address of the location to be programmed is loaded into the programming unit. Then, at step 104, that location is programmed according to the fixed pulse width, e.g., as may be specified by the manufacture of the programmable device. The programming step is verified at step 106. During verification, the addressed location is checked to determine whether programming was successful. If so, the check is made at step 108 to determine whether this was the last location in the programmable device to be programmed. When all such locations have been programmed, the process quits at step 110. If an attempted programming of a particular location was not successful, then at step 112, a check is made to determine whether the programming operation has exceeded a predetermined number of attempts to program that location. If not, another attempt is made to program the location according to the fixed pulse width. If, after several attempts, the location still has not been programmed, the programmable device fails the programming operation at step 114.
Conventional programming methods, such as that described above, typically fail to account for process variations among different lots of programmable devices. As a result, the fixed programming pulse width may be inadequate to assure programming of all locations in the programmable device. Or, the fixed programming pulse width may exceed the time necessary to adequately program the non-volatile memory cells. Either case presents a problem. For example, where the programming pulse width is not long enough, otherwise useful devices may be rejected because they fail repeated programming attempts. Alternatively, where the programming pulse width is to long, repeated programming and erase operations may cause early failure of the memory cells (e.g., due to oxide break down in the presence of strong electric fields caused by the programming and/or erase voltages). Thus, the use of fixed programming parameters (such as pulse widths) for programmable devices presents a less than ideal solution.